The present invention relates to parallel analog-to-digital converters and, more particularly, to a technique for reducing or eliminating output errors caused by ambiguities occurring in outputs of comparators and decoding circuitry logic gates used in the converters.
Analog-to-digital converters of many kinds are increasingly being used in more kinds of situations and equipment. This increase in use has occurred because the cost of integrated circuits has decreased while the rate and accuracy performance thereof has increased. This increase in capability has brought even greater demand for better performance, including ever faster operating analog-to-digital converters
In analog-to-digital converters, increases in conversion rate often come at the expense of converter accuracy. In general, the parallel, or flash, analog-to-digital converter is the design currently permitting the fastest conversion rate. The ability of the parallel analog-to-digital converter to perform fast conversion arises through its ability to sample any analog input signal in the converter's input signal range in one short clock cycle. Conversion rates are further increased by minimizing the number of circuit components along the signal paths to the converter's output taken by the converter internal signals during the conversion of an analog sample value into its digital equivalent.
One way to minimize the number of circuit components in a flash converter decoding circuit is through use of decoding circuitry implementing the so called "thermometer code". Implementation of the thermometer code requires providing a first level of logic gates connected to the comparator outputs with these gates providing a sequence of outputs. Each gate output corresponds to one comparators in a sequence of comparators each of which has a higher reference voltage on its reference input than the preceding one. The thermometer code corresponds to providing a logic state on an output of one of the logic gates that differs from the logic states provided on all other gate outputs, this selected gate being the gate corresponding to the last comparator in the sequence of comparators having its reference level exceeded by the system analog input voltage signal provided commonly on the signal inputs of the comparator.
This arrangement can be seen in the analog-to-digital converter 10 of FIG. 1 showing an arbitrarily chosen number of comparators, 50, 80, 110, 140, 170, 200, and 230, in a sequence. The reference voltage inputs of these comparators are the inputs, 54, 84, 114, 144, 174, 204, and 234, respectively, each of which is connected to a monotonically increasing sequence of voltage reference values. These values are established by a reference voltage source applied between a pair of voltage source terminals, 12 and 14, and a voltage divider network also between these terminals formed by series-connected set of resistors, 52, 82, 112, 142, 172, 202, 232 and 262. Each of the non-inverting comparator inputs 56, 86, 116, 146, 176, 206, and 236, is connected to the system analog voltage signal input, 16. Each comparator has a primary output, 24, on the upper diagonal side thereof and a complementary output, 22, on its lower diagonal side. Each comparator has a clock input (not shown) on which it receives periodic clock pulses corresponding to the desired sampling rate. The outputs of each of the comparators are held at the value occurring at the beginning of a clock pulse for the remainder of the clock pulse.
If the input voltage on the non-inverting input 20 of a comparator is sufficiently less than the reference voltage on the inverting input 18 of the comparator, the comparator's primary output has a low logic state voltage level thereon and its complementary output 22 has a high logic state voltage level thereon. If, on the other hand, the input voltage exceeds the reference voltage by a sufficient amount, the primary output 24 has a high logic state voltage level thereon and the complementary output 22 has a low logic state voltage level thereon.
From the outputs of the comparators, following the rules of operation therefor described above, the thermometer code can be implemented using a sequence of two input AND logic gates 60, 90, 120, 150, 180, and 210, with one corresponding to each comparator, that provide a first level of logic gates. Each AND gate in FIG. 1 has one input thereof, 26, connected to primary output 24 of one comparator in the sequence thereof, and another input, 28, connected to complementary output 22 of the next succeeding comparator in that sequence. As is well known, the output of an AND logic gate will be at a high logic voltage level only if all of its inputs are also at a high logic voltage level. For the first level of AND gates connected as in FIG. 1, this occurs if both the primary output of the comparator to which it is connected and the complementary output of the next succeeding comparator to which it is also connected both provide high logic voltage levels.
In operation, this results in only one of the AND logic gate outputs 30 providing a high logic state voltage level, and each of the remaining AND logic gate outputs 30 providing a low logic state voltage level. This one gate will be the one that corresponds to the comparator in the sequence thereof having the largest reference voltage connected thereto that is sufficiently less in voltage level than the system input analog signal voltage.
The outputs 30 of the AND logic gates are shown in FIG. 1 connected to a binary decoder comprising a set of OR logic gates, 236, 240 and 244, which form a second level of logic gates. Again, as is well known for an OR gate, the occurrence of a high logic state voltage level on any of the inputs of an OR logic gate will place the output thereof in the same high logic state voltage level. These OR logic gates 236, 240, 244 have outputs 238, 242, and 246, respectively, on each of which there is provided a logic state signal forming a digit signal indicating the value of a digit for the binary number representation provided when all of the digit signals on outputs 238, 242 and 246 are considered together. The binary number represented by a particular set of logic values occurring in the digit signals will have a value corresponding to the amplitude of the voltage signal occurring on the system analog voltage signal input 16 and giving rise to the binary representation.
The output 30 of each first logic level AND gate 60, 90, 120, 150, 180, or 210 is connected to an input of selected ones of the second logic level OR gates 236, 240, or 244. These are just those gates state on output 222 thereof when the comparator corresponding to the AND gate connected thereto has a reference voltage on its inverting input 18 less than the voltage on its non-inverting input 24 from voltage applied to the system analog voltage signal input 16.
One type of error which may occur in the parallel analog-to-digital converter of FIG. 1 occurs when the input voltage signal applied to system analog voltage signal input 16 to the non-inverting input 20 of each comparator, is very nearly equal to the reference voltage applied to one of the non-inverting inputs 18 of one of the comparators. If this occurs with a sufficiently small difference between these two voltage levels, the logic levels on the primary and complementary outputs 22 and 24, respectively, of that comparator are undefined, i.e. they may be anywhere between the low and high logic state voltage levels and thus provide an ambiguous or indefinite logic voltage level. Such result is likely to further result in erroneous logic voltage levels being present on outputs 238, 242 and 246 of each of OR gates 236, 240 and 244, respectively.
Thus, there is desired a parallel analog-to-digital converter that avoids such output errors, or at least limits the extent thereof, if an indefinite voltage level occurs on a comparator output 238, 242 or 244, but without sacrificing the sample conversion rate of the converter.